The actual schematic inside this block — every part is explained below.
555 Timer (astable)
The most famous chip in hobby electronics, in its most famous job: a square-wave oscillator
that needs only two resistors and a capacitor to set its rhythm.
The trick inside: the 555 watches C1's voltage and bounces it between two trip points —
1/3 and 2/3 of VCC — forever:
C1 charges through Ra + Rb toward VCC. Output is HIGH.
At 2/3·VCC the threshold comparator flips the internal latch: output LOW, and pin 7
(DIS) opens a path to ground.
C1 now discharges through only Rb into pin 7. At 1/3·VCC the trigger comparator
flips everything back. Repeat until the heat death of the universe.
f ≈ 1.44 / ((Ra + 2Rb) · C1) — and because charge flows through Ra+Rb but discharge only
through Rb, the HIGH half is always longer: duty = (Ra+Rb)/(Ra+2Rb). Want closer to 50%?
Make Rb ≫ Ra.
C2 quiets the CONTROL pin — that pin is literally a tap on the internal 2/3·VCC
divider, so supply noise there jitters your frequency.
RST is tied to VCC: a floating reset pin is the classic "my 555 randomly stops" bug.
Exposes:vcc (4.5–15 V), out (square wave, can source/sink a beefy 200 mA), gnd.
⚠ The trip points scale WITH the supply — that's why the frequency barely cares about
VCC. But it also means a sagging battery changes the absolute thresholds; on the bipolar
NE555 expect supply spikes when the output switches (the totem-pole shoots through) —
bypass VCC well.
Exposed nets
●vccin · power · 4.5–15 V
●gndin · gnd
●outout · signal
Inside this block
U1
ne555
the timer — two comparators and a latch that bounce C1's voltage between 1/3 and 2/3 of VCC forever
Ra
10k
charges C1 (with Rb) toward VCC — sets the HIGH half of the period
Rb
47k
C1 discharges through ONLY this into pin 7 — sets the LOW half
C1
10nF
the timing capacitor — its sawtooth between the two trip points IS the oscillation
C2
10nF
quiets the CONTROL pin's internal 2/3·VCC reference
Inside the chip: 555 timer — two comparators, a latch, and a discharge switch
What U1 actually does, drawn out in discrete parts — the same view the editor's “break into discrete” shows.
The most famous chip in electronics, opened up. R1–R3 are the three equal resistors the '555' is named for — they tap 1/3 and 2/3 of VCC. Comparator A trips when THR passes 2/3·VCC (resetting the latch), comparator B when TRG drops under 1/3·VCC (setting it). The latch's inverted output turns the discharge transistor on whenever the output is low. CV is literally the 2/3 tap — that's why decoupling it steadies the frequency. Simplified honestly: the latch is drawn as a logic block (itself two cross-coupled transistors), RST is wired into the reset line without its real priority logic, and the output buffer is omitted.
Limits & gotchas
⚠f.formula 0 — f ≈ 1.44 / ((Ra + 2·Rb) · C1). The values here (10k + 2×47k, 10nF) give ~1.4 kHz; duty = (Ra+Rb)/(Ra+2Rb) ≈ 55% — duty can never reach 50% exactly in this basic astable (Ra must be > 0).
⚠c2.note 0 — C2 on the CONTROL pin isn't optional decoration — the pin sits at an internal 2/3·VCC divider tap, and supply noise there jitters the threshold. 10 nF quiets it.
Use this block in a real design
Drop it on a canvas, wire it up, and watch the live checks — free, no card.